1. Field of the Invention
This invention relates to a computer system and, more particularly to memory request queue logic combined with a memory controller to present streams of memory read or memory write requests to system memory according to one of three programmable modes of operation.
2. Description of the Related Art
Modern personal computers are often called upon to perform at increasingly higher levels. For example, many desktop and portable personal computers may employ a high speed central processing unit ("CPU") and multiple busses between the CPU and numerous peripheral devices. Multiple busses may include a CPU local bus connected between the CPU, a peripheral bus connected to slower peripheral (or I/O) devices, and a mezzanine bus connected between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture ("ISA") bus, and enhanced ISA ("EISA") bus or a microchannel bus. The mezzanine bus can, alternatively, be considered a peripheral component interface ("PCI") bus to which higher speed input/output devices can be connected.
Coupled between the various busses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the "north bridge". Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the "south bridge".
When accommodating various busses, a modern north bridge allows accesses to and from a computer main memory (or system memory) connected to the north bridge. Thus, a north bridge may comprise a memory controller for controlling, e.g., a dynamic random access memory ("DRAM"). DRAM architecture is generally well known, and includes an array of storage cells. Access to the storage cells is accomplished by dividing an address signal into two parts and multiplexing them onto the row and column address pins of the memory array. When row address strobe ("RAS") is active, the row address latch in row decoder of the DRAM allows selection of one row within the array. When the column address strobe ("CAS") is asserted, the column address is decoded and latched to one of multiple sense amplifiers arranged across the column of the array. The state of write enable ("WE") signal determines whether data is read ("DOUT") or written ("DIN").
Most DRAMs support various access modes including, for example, page mode, static-column mode, as well as various high-speed refresh and pre-charge mechanisms. Page mode or static mode came about in an effort to enhance the speed of DRAMs relative to the CPU. Essentially, page mode and static-column mode help minimize wait states (i.e., times at which the CPU is suspended in order to allow the memory to catch up with the CPU).
Another technique for minimizing wait states is to separate the DRAM into two or more banks. Data held in alternate banks allows the CPU to access the alternate banks when it reads sequential bytes. When one bank is read, the other may be cycling so that the CPU does not have to wait.
The combination of page mode, static-column mode, and banked memory helps enhance the throughput or bandwidth of the memory bus coupled between the memory controller and the system memory. Another enhancement to bandwidth includes the recent advances into synchronous DRAM ("SDRAM"). Essentially, SDRAM synchronizes all address, data and control signals with a single system clock. The system lock is preferably the same clock which operates the CPU bus up to, for example 100 Hz. An SDRAM offers substantial advantages over asynchronous DRAMs. For example, asynchronous DRAMs do not allow access to a row within the array until a previous row access is completed. By contrast, an SDRAM includes separate commands for accessing and pre-charging multiple rows of storage cells in the array. Once row and column addresses are provided to an SDRAM having multiple bank arrays, a banked memory array which is accessed remains active. The selected row remains open until a pre-charge command precharges the selected row in the memory array.
Recent advances in high speed memory access allows "like" accesses to be performed more efficiently, essentially in a back-to-back manner. For example, if a sequence of read requests are presented to the memory, the read request can be more quickly serviced than if they are not interspersed with write request, regardless of whether the read requests are in the same bank or page. Thus, similar types of request (i.e., all reads versus all writes) can be more readily pipelined through the memory bus if, for example, a read request is not followed by a write and then by another read.
Breaking read requests (or write request) with write requests (or read request) reduces the pipeline efficiency of the memory bus due to SDRAM read/write or write/read idle time requirements. The idle time between reads and writes, or writes and reads, consumes bandwidth and temporarily breaks the pipeline. A mechanism which can more optimally arrange a stream of read request or write request would therefore improve the memory bus bandwidth. This improvement will be further enhanced if the memory controller is in page mode or if banked memory is implemented, for example. The desired technique of streaming like requests may, however, require queuing the request and cross snooping between read and write request to prevent corruption.